Viavi Xgig Protocol Analysis
The Viavi Xgig-6P16 platform provides PCIe/NVMe/CXL protocol analysis and exerciser functionality for debugging and compliance testing at all PCIe speeds including Gen 4, Gen 5 and Gen 6 with PAM-4 signalling.
The Analyser allows a detailed view of traffic between a host and endpoint device, supporting PCIe FLIT Mode, Non-Flit Mode, CXL, and NVMe.
Link Exerciser & Repeatable Control
The Exerciser is an essential tool for debugging difficult protocol communication problems because it provides full, bit-level, repeatable control for generated PCIe 6.0, CXL and NVMe data traffic.
Users can set Exerciser link rates and widths and control transitions to other rates. The fully integrated Analyser/Exerciser architecture enables a variety of test conditions, such as injecting corrupted ordered sets or error bytes to verify receiver device recovery behavior.
Key Technical Capabilities
- check_circlePCIe 6.0 FLIT Mode Error Injection and Recovery Analysis
- check_circlePort Bifurcation and Simultaneous Multi-User Capability
- check_circleTroubleshooting Complex LTSSM Transactions
- check_circleSupports all PCIe speeds up to Gen 6, 64GTps (Gen 7 coming soon)
- check_circlePCI-SIG Approved for Compliance and Interoperability testing
- check_circleUser can set Exerciser link rates/widths and control transitions to other rates
- check_circleSupport for new PCIe FLIT Mode, FEC and TS0 Ordered Set
Symmetric PCIe Generation Matrix
| PCIe Gen Speed | Lane Link Rate | Modulation Signalling | FLIT Mode Support | FEC Error Correction | Max Raw Bandwidth (x16) |
|---|---|---|---|---|---|
| PCIe Gen 4 | 16 GT/s | NRZ (Non-Return-to-Zero) | Not Supported | Not Required | 64 GB/s |
| PCIe Gen 5 | 32 GT/s | NRZ (Non-Return-to-Zero) | Not Supported | Not Required | 128 GB/s |
| PCIe Gen 6 | 64 GT/s | PAM-4 (Pulse Amplitude Modulation) | Supported (FLIT Mode) | Required (Forward Error Correction) | 256 GB/s |
LTSSM Transition Tracker
History Log EnabledNormal operational state where system data, memory read/write TLPs, and DLLPs are transmitted.
Xgig Software Suite
Expert™
Post-capture analysis tool that automatically scans traces to flag protocol violations and identify performance bottlenecks.
Serialytics™
Interactive debug software providing graphical analytics of complex PCIe links, making it easy to drill down to individual packets.
MLTT
Multi-Link Test Tool simulating complex multi-host, multi-root configurations to validate bifurcation behavior under load.
PCIe Unidirectional Bandwidth Planner
Evaluate maximum aggregate bandwidth, line-rates, and FEC requirements based on generation speeds and lane widths.
tuneHardware Configuration
calculateLink Recommendation Report
Ready to test your next-generation silicon interfaces?
Our compliance engineers are ready to demonstrate the Viavi Xgig-6P16 platform under complex bifurcation and injection scenarios.
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