PCIe Gen5 Exerciser

Supports all PCIe speeds up to Gen5

 PCIe Gen5 Exerciser

The Xgig Gen5 Exerciser enables in-depth protocol evaluation and debugging at 32 Gbps per lane, as well as testing for PCIe compliance, allowing development of network technologies to meet the demands of tomorrow’s high speed, high performance computing applications.  With a modular architecture and an implementation tightly coupled to a fully-featured analysis system, the exerciser reduces the need for extra hardware investments while a familiar management interface helps limit training needs, minimising the overall design and development costs.

Key features include:

  • Generates and responds to PCIe compliant packest
  • Operates to 32 GT/s and supports all other PCIe data rates of 2.5, 5.0, 8.0 and 16 GT/s
  • Supports link widths of 1, 2, 4, 8 and 16 lanes
  • Tightly aligned operation with the XGIG analyser for fully detailed bit level trace captures
  • Runs the PCIe compliance test suite
  • Performs LTSSM testing:  both positive and negative test senarios
  • LTSSM state tracker with history log
  • Define and save custom test configurations and test suites
  • Define, modify and send Ordered Sets
  • Scripting API allows complex test cases
  • Runs on the Viavi XGIG 5P16 platform
  • Field replaceable fan and power supply assemblies
  • Works with the XGIG Gen5 host test stand

Also available:

PCIe/NVMe Protocol Analyser and Jammer Solutions

Find out more about

PCIe Gen5 Exerciser:

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